Selective dummy writes for asynchronous power loss handling in memory devices

ABSTRACT

An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.17/007,539, filed Aug. 31, 2020, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systemsand, more specifically, to asynchronous power loss (APL) handling in amemory sub-system.

BACKGROUND

A memory sub-system can include one or more memory devices that storedata. The memory components can be, for example, non-volatile memorydevices and volatile memory devices. In general, a host system canutilize a memory sub-system to store data at the memory devices and toretrieve data from the memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousembodiments of the disclosure.

FIG. 1 is a block diagram illustrating an example computing system thatincludes a memory sub-system, in accordance with some embodiments of thepresent disclosure.

FIG. 2 is a diagram illustrating interactions between components of thememory sub-system in handling an APL event, in accordance with someembodiments of the present disclosure.

FIG. 3 is a graph illustrating an example voltage threshold distributionin a memory device cell, in accordance with some embodiments of thepresent disclosure.

FIGS. 4 and 5 are flow diagrams illustrating an example method for APLhandling in a memory sub-system, in accordance with some embodiments ofthe present disclosure.

FIG. 6 is a block diagram of an example computer system in whichembodiments of the present disclosure may operate.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to selectively performingdummy write operations on an APL affected memory device in a memorysub-system. A memory sub-system can be a storage device, a memorymodule, or a hybrid of a storage device and memory module. Examples ofstorage devices and memory modules are described below in conjunctionwith FIG. 1 . In general, a host system can utilize a memory sub-systemthat includes one or more components, such as memory devices that storedata. The host system can provide data to be stored at the memorysub-system and can request data to be retrieved from the memorysub-system.

A memory device can be a non-volatile memory device. One example ofnon-volatile memory devices is a negative-and (NAND) memory device.Other examples of non-volatile memory devices are described below inconjunction with FIG. 1 . Data operations can be performed by the memorysub-system. The data operations can be host-initiated operations. Forexample, the host system can initiate a data operation (e.g., write,read, erase, etc.) on a memory sub-system. The host system can sendaccess requests (e.g., write command, read command) to the memorysub-system, such as to store data on a memory device at the memorysub-system and to read data from the memory device on the memorysub-system.

Some memory devices (e.g., NAND memory devices) include an array ofmemory cells (e.g., flash cells) to store data. Each cell includes atransistor and within each cell, data is stored as the threshold voltageof the transistor, based on the logical value the cell represents (e.g.,0 or 1). During a read operation, a read reference voltage is applied tothe transistor to determine the logical value it represents, if any.Memory cells in these devices can be grouped as pages that can refer toa logical unit of the memory device used to store data. With some typesof memory devices (e.g., NAND), pages are grouped to form blocks (alsoreferred to herein as “memory blocks”).

As used herein, asynchronous power loss (APL), refers to an unexpectedloss of power in a memory sub-system. For example, APL may occur whenthe power source for the memory sub-system dips below a certain voltagethreshold and ongoing operations in a memory device in the memorysub-system (e.g., erase, program or read) are interrupted. When an APLevent occurs during memory device write operations, different cell typesmay appear programmed or erased when a read operation is performed,depending on how far along the programming was before it was interruptedby the APL event. Write operations in a memory sub-system are performedin a logical sequence defined by an internally maintained writetranslation table so it is inconsistent with internal system logic forerased pages to be present in a block that is supposedly fully written.Page scan operations also rely on the sequential nature of writeoperations, so if any page is unexpectedly read as erased, the memorysub-system attempts to recover data stored at the memory location usingtraditional error handling techniques and eventually using redundantarray of independent NAND (RAIN) techniques. This scenario not onlybreaks the scan logic in the memory sub-system but also results in avery high latency within the memory sub-system.

When an APL event occurs during memory device write operations,partially written or erased pages may appear programmed or erased when aread operation is performed, depending on how far along the programmingwas before it was interrupted by the APL event. Conventional techniquesfor APL handling involve moving committed data in an APL affected blockto a new block and erasing the APL affected block. With the increase innumber of pages in a block, moving committed data and erasing the APLblock impact Time-To-Ready (TTR) design constraints.

One approach to handling APL events that interrupt memory device writeoperations is to write dummy data (e.g., nonce data) to the APL affectedpages to ensure that the APL affect pages are sufficiently programmed sothat subsequent read operations performed on the pages returnuncorrectable error correcting code (UECC) rather than an erased status.However, writing dummy data on top of a previously written or partiallywritten page can cause program disturb errors and state level wideningon previously written pages in the same wordline. Aspects of the presentdisclosure address APL events in memory sub-systems by selectivelywriting dummy data to APL affected pages of a memory device. At systeminitialization, an APL handling component of the memory sub-systemdetermines the previous power loss is an APL event that interrupted awrite operation at the memory device. Based on detecting the APL event,the APL handling component identifies a last written page in the memorydevice and determines a count of zeros programmed in the last writtenpage. The APL handling component compares the count of zeros to athreshold constraint. If the count of zeros satisfies the constraint,the APL handling component determines that the last written page issufficiently programmed and completes APL recovery processes withoutperforming a dummy write on the last written page. If the count does notsatisfy the threshold constraint, the APL handling component performsthe dummy write operation on the last written page.

By writing dummy data to APL affected pages, the APL handling componentensures that APL affected pages can be reliably read back as UECC.Further, by selectively writing dummy data based on whether a page issufficiently programmed, the APL handling component reduces the numberof dummy write operations performed, thereby reducing, if noteliminating, program disturb errors and state level widening problemsthat can be caused by back-to-back APL scenarios.

FIG. 1 illustrates an example computing system 100 that includes amemory sub-system 110, in accordance with some embodiments of thepresent disclosure. The memory sub-system 110 can include media, such asone or more volatile memory devices (e.g., memory device 140), one ormore non-volatile memory devices (e.g., memory device 130), or acombination of such.

A memory sub-system 110 can be a storage device, a memory module, or ahybrid of a storage device and memory module. Examples of a storagedevice include a solid-state drive (SSD), a flash drive, a universalserial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC)drive, a Universal Flash Storage (UFS) drive, a secure digital (SD)card, and a hard disk drive (HDD). Examples of memory modules include adual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), andvarious types of non-volatile dual in-line memory module (NVDIMM).

The computing system 100 can be a computing device such as a desktopcomputer, laptop computer, network server, mobile device, a vehicle(e.g., airplane, drone, train, automobile, or other conveyance),Internet of Things (IoT) enabled device, embedded computer (e.g., oneincluded in a vehicle, industrial equipment, or a networked commercialdevice), or such computing device that includes memory and a processingdevice.

The computing system 100 can include a host system 120 that is coupledto one or more memory sub-systems 110. In some embodiments, the hostsystem 120 is coupled to different types of memory sub-system 110. FIG.1 illustrates one example of a host system 120 coupled to one memorysub-system 110. As used herein, “coupled to” or “coupled with” generallyrefers to a connection between components, which can be an indirectcommunicative connection or direct communicative connection (e.g.,without intervening components), whether wired or wireless, includingconnections such as electrical, optical, magnetic, and the like.

The host system 120 can include a processor chipset and a software stackexecuted by the processor chipset. The processor chipset can include oneor more cores, one or more caches, a memory controller (e.g., NVDIMMcontroller), and a storage protocol controller (e.g., peripheralcomponent interconnect express (PCIe) controller, serial advancedtechnology attachment (SATA) controller). The host system 120 uses thememory sub-system 110, for example, to write data to the memorysub-system 110 and read data from the memory sub-system 110.

The host system 120 can be coupled to the memory sub-system 110 via ahost interface. Examples of a host interface include, but are notlimited to, a SATA interface, a PCIe interface, USB interface, FibreChannel, Serial Attached SCSI (SAS), Small Computer System Interface(SCSI), a double data rate (DDR) memory bus, a DIMM interface (e.g.,DIMM socket interface that supports Double Data Rate (DDR)), Open NANDFlash Interface (ONFI), Double Data Rate (DDR), Low Power Double DataRate (LPDDR), or any other interface. The host interface can be used totransmit data between the host system 120 and the memory sub-system 110.The host system 120 can further utilize an NVM Express (NVMe) interfaceto access components (e.g., memory devices 130) when the memorysub-system 110 is coupled with the host system 120 by the PCIeinterface. The host interface can provide an interface for passingcontrol, address, data, and other signals between the memory sub-system110 and the host system 120. FIG. 1 illustrates a memory sub-system 110as an example. In general, the host system 120 can access multiplememory sub-systems via a same communication connection, multipleseparate communication connections, and/or a combination ofcommunication connections.

The memory devices 130,140 can include any combination of the differenttypes of non-volatile memory devices and/or volatile memory devices. Thevolatile memory devices (e.g., memory device 140) can be, but are notlimited to, random access memory (RAM), such as dynamic random accessmemory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device 130)include negative-and (NAND) type flash memory and write-in-place memory,such as a three-dimensional (3D) cross-point memory device, which is across-point array of non-volatile memory cells. A cross-point array ofnon-volatile memory can perform bit storage based on a change of bulkresistance, in conjunction with a stackable cross-gridded data accessarray. Additionally, in contrast to many flash-based memories,cross-point non-volatile memory can perform a write in-place operation,where a non-volatile memory cell can be programmed without thenon-volatile memory cell being previously erased. NAND type flash memoryincludes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

Each of the memory devices 130 can include one or more arrays of memorycells. One type of memory cell, for example, single level cells (SLC),can store one bit per cell. Other types of memory cells, such asmulti-level cells (MLCs), triple level cells (TLCs), quad-level cells(QLCs), and penta-level cells (PLCs) can store multiple bits per cell.In some embodiments, each of the memory devices 130 can include one ormore arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or anycombination of such. In some embodiments, a particular memory device caninclude an SLC portion, and an MLC portion, a TLC portion, a QLCportion, or a PLC portion of memory cells. The memory cells of thememory devices 130 can be grouped as pages that can refer to a logicalunit of the memory device used to store data. With some types of memory(e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory components such as NAND type flash memory(e.g., 2D NAND, 3D NAND) and 3D cross-point array of non-volatile memorycells are described, the memory device 130 can be based on any othertype of non-volatile memory, such as read-only memory (ROM), phasechange memory (PCM), self-selecting memory, other chalcogenide basedmemories, ferroelectric transistor random-access memory (FeTRAM),ferroelectric random access memory (FeRAM), magneto random access memory(MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM(CBRAM), resistive random access memory (RRAM), oxide based RRAM(OxRAM), NOR flash memory, and electrically erasable programmableread-only memory (EEPROM).

A memory sub-system controller 115 (or controller 115 for simplicity)can communicate with the memory devices 130 to perform operations suchas reading data, writing data, or erasing data at the memory devices 130and other such operations. The memory sub-system controller 115 caninclude hardware such as one or more integrated circuits and/or discretecomponents, a buffer memory, or a combination thereof. The hardware caninclude digital circuitry with dedicated (i.e., hard-coded) logic toperform the operations described herein. The memory sub-systemcontroller 115 can be a microcontroller, special purpose logic circuitry(e.g., a field programmable gate array (FPGA), an application specificintegrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller 115 can include a processor 117(processing device) configured to execute instructions stored in a localmemory 119. In the illustrated example, the local memory 119 of thememory sub-system controller 115 includes an embedded memory configuredto store instructions for performing various processes, operations,logic flows, and routines that control operation of the memorysub-system 110, including handling communications between the memorysub-system 110 and the host system 120.

In some embodiments, the local memory 119 can include memory registersstoring memory pointers, fetched data, and the like. The local memory119 can also include ROM for storing micro-code. While the examplememory sub-system 110 in FIG. 1 has been illustrated as including thememory sub-system controller 115, in another embodiment of the presentdisclosure, a memory sub-system 110 does not include a memory sub-systemcontroller 115, and can instead rely upon external control (e.g.,provided by an external host, or by a processor or controller separatefrom the memory sub-system).

In general, the memory sub-system controller 115 can receive commands oroperations from the host system 120 and can convert the commands oroperations into instructions or appropriate commands to achieve thedesired access to the memory devices 130 and/or the memory device 140.The memory sub-system controller 115 can be responsible for otheroperations such as wear leveling operations, garbage collectionoperations, error detection and ECC operations, encryption operations,caching operations, and address translations between a logical address(e.g., logical block address (LBA), namespace) and a physical address(e.g., physical block address) that are associated with the memorydevices 130. The memory sub-system controller 115 can further includehost interface circuitry to communicate with the host system 120 via thephysical host interface. The host interface circuitry can convert thecommands received from the host system 120 into command instructions toaccess the memory devices 130 and/or the memory device 140 and convertresponses associated with the memory devices 130 and/or the memorydevice 140 into information for the host system 120.

In some embodiments, the memory devices 130 include local mediacontroller 135 that operates in conjunction with memory sub-systemcontroller 115 to execute operations on one or more memory cells of thememory devices 130.

The memory sub-system 110 also includes an asynchronous power loss (APL)handling component 113 that is responsible handling APL events withinthe memory sub-system 110. APL handling includes two phases: 1) APLdetection and 2) APL recovery. During APL detection, the APL handlingcomponent 113 determines whether a previous system power down is normalor unexpected. APL detection is performed as part of initialization ofthe memory device 130. The APL handling component 113 uses specializedread operations and system flag checks to determine if an APL eventoccurred. During the APL recovery phase, the APL handling component 113ensures data committed to the memory device 130 are intact and corrupteddata is recovered. As part of the APL recovery phase, the APL handlingcomponent 113 can write dummy data to pages of the memory device 130that are affected by the APL event (hereinafter also referred to as “APLaffected pages”). The APL handling component selectively performs dummywrite operations based on whether the APL handling component determinesa page is sufficiently programmed based on a number of zeros programmedin the page. Further details regarding dummy write operations by the APLhandling component 113 are discussed below.

In some embodiments, the memory sub-system controller 115 includes atleast a portion of the APL handling component 113. For example, thememory sub-system controller 115 can include a processor 117 (processingdevice) configured to execute instructions stored in local memory 119for performing the operations described herein. In some embodiments, theAPL handling component 113 is part of the host system 120, anapplication, or an operating system. In some embodiments, the localmedia controller 135 includes at least a portion of the APL handlingcomponent 113.

FIG. 2 is a data flow diagram illustrating interactions betweencomponents of the memory sub-system in handling an APL event, inaccordance with some embodiments of the present disclosure. In theexample illustrated in FIG. 2 , the memory device 130 is a NAND memorydevice including multiple blocks. For example, as shown, a NAND block201 includes an array of NAND cells that includes pages (rows) andstrings (columns). Each cell includes a transistor and within each cell,data is stored as the threshold voltage of the transistor, based on thelogical value of the cell (e.g., 0 or 1). During a read operation, aread reference voltage is applied to the transistor, and if the readreference voltage is higher than the threshold voltage of the cell, thetransistor is programmed and is recognized by a memory sub-system as abinary value of 0. If the read reference voltage is lower than thethreshold voltage of the cell, the transistor is recognized as a binaryvalue of 1.

Strings are connected within the NAND block to allow storage andretrieval of data from selected cells. NAND cells in the same column areconnected in series to form a bit line (BL). All cells in a bit line areconnected to a common ground on one end and a common sense amplifier onthe other for reading the threshold voltage of one of the cells whendecoding data. NAND cells are connected horizontally at their controlgates to a word line (WL) to form a page. A page is a set of connectedcells that share the same word line and is the minimum unit to program.

Upon initialization of the memory sub-system 110 at 200, the APLhandling component 113 determines whether a previous system power downwas a normal system power down or an APL event. To determine if theprevious power down is an APL event, the APL handling component 113performs specialized read operations and system flag checks. Forexample, the APL handling component 113 can obtain data from the memorydevice 130 (e.g., using one or more commands) that indicates whether apower loss occurred, whether a page is fully erased, partially erased,fully programmed or partially programmed, and whether programming of apage was interrupted prematurely.

Based on detecting the APL event, the APL handling component 113 queriesthe memory device 130 to identify the last written page (LWP), at 204.Within the memory device 130, write operations are performedsequentially according to an internal table referred to as a writetranslation table. The LWP is identified based on the write translationtable.

The APL handling component 113 analyzes the LWP to determine whether theLWP is sufficiently programmed to avoid performing a dummy writeoperation on the LWP. To this end, the APL handling component 113 countsthe zeros programmed into the LWP, at 206, and compares the count to athreshold constraint, at 208. The APL handling component 113 candetermine the count of zeros by applying a read reference voltage tocells in the page. If the read reference voltage is higher than thethreshold voltage of the cell, the cell is recognized by the APLhandling component 113 as being programmed with a zero. As will bediscussed in further detail below, each page type has one or moreassociated read levels, and the read level associated with the page typedetermine the read reference voltage applied to the page during normalread operations. In counting zeros programmed in the LWP, the APLhandling component 113 shifts the read levels such that the readreference voltage applied at every level is decreased relative todefault read levels.

If the count satisfies the threshold condition (e.g., the count of zerosis greater than a threshold value), the APL handling component 113 doesnot perform at dummy write operation as the LWP is sufficientlyprogrammed (210). If the count does not satisfy the threshold condition(e.g., the count of zeros is less than the threshold value), the APLhandling component 113 writes dummy data to the LWP.

With reference to FIG. 3 , an example threshold voltage distribution ina 3-bit TLC NAND flash cell. As noted above, each NAND cell stores datain the form of a threshold voltage (V_(th)), the lowest voltage at whichthe cell can be turned on. With reference to FIG. 3 , the thresholdvoltage range of a 3-bit TLC is divided into eight regions by sevenreference voltages V₁, V₂, V₃, V₄, V₅, V₆, and V₇. The referencevoltages V₁, V₂, V₃, V₄, V₅, V₆, and V₇ are also referred to “readlevels”. The region in which the threshold voltage of the cellrepresents the current state of the cell. As shown, the state of a TLCNAND flash cell is one of the following: ER (erased), P1, P2, P3, P4,P5, P6 or P7. Each cell state decodes into a 3-bit value that is storedin the flash cell (e.g., 111, 110, 100, 000, 010, 011, 001, and 101).The threshold voltage of all cells in the memory device 130 is boundedby an upper limit: Vpass, which is the pass-through voltage.

As discussed above, NAND cells in the memory device 130 are organizedinto arrays, referred to as blocks (e.g., NAND block 201), and withineach block, cells in the same row share a wordline (WL). The leastsignificant bits (LSB) stored in a wordline form a lower page (LP), themost significant bits (MSB) stored in a wordline form an upper page(UP), and the middle bits stored in a wordline form an extra page (XP).

During a read operation, a read reference voltage (Vref) selected fromread levels V₁, V₂, V₃, V₄, V₅, V₆, and V₇ is applied one or more timesto the wordline that contains the data to be read. The read level useddepends on which page type (e.g., LP, UP, or XP) is being read andunless modified, are based on default read levels associated with eachpage type. As an example, to read an LP page, read reference voltages V₁and V5 are applied. If a cell turns off when V₁ is applied and turns onwhen V5 is applied, the cell contains a threshold voltage V_(th) whereV₁<Vth<V₅, indicating that it is in either the P1, P2, P3, or P4 stateand holds an LSB value of 0. Otherwise, if the cell is on when V1 isapplied or off when V5 is applied, the cell is in the ER, P5, P6, or P7state, holding an LSB value of 1.

FIGS. 4 and 5 are flow diagrams illustrating an example method 400 forAPL handling in a memory sub-system (e.g., the memory sub-system 110) inaccordance with some embodiments of the present disclosure. The method400 can be performed by processing logic that can include hardware(e.g., a processing device, circuitry, dedicated logic, programmablelogic, microcode, hardware of a device, an integrated circuit, etc.),software (e.g., instructions run or executed on a processing device), ora combination thereof. In some embodiments, the method 400 is performedby the APL handling component 113 of FIG. 1 . Although processes areshown in a particular sequence or order, unless otherwise specified, theorder of the processes can be modified. Thus, the illustratedembodiments should be understood only as examples, and the illustratedprocesses can be performed in a different order, and some processes canbe performed in parallel. Additionally, one or more processes can beomitted in various embodiments. Thus, not all processes are required inevery embodiment. Other process flows are possible.

At operation 405, the processing device detects an APL event thatoccurred at a memory device (e.g., the memory device 130) while a writeoperation was being performed. That is, the processing device determinesthat a previous power loss that interrupted a write operation was an APLevent. In detecting the APL event, the processing device performsspecialized read operations and system flag checks. For example, theprocessing device can obtain data from the memory device that indicateswhether a power loss occurred, whether a page is fully erased, partiallyerased, fully programmed or partially programmed, and whetherprogramming of a page was interrupted prematurely.

In response to detecting the APL event at the memory device, theprocessing device identifies a LWP in the memory device, at operation410. The processing device can determine the LWP based on an internaltable used to track write operations. Depending on the embodiment, theprocessing device can maintain the internal table or the processingdevice can obtain this information from the memory device using one ormore commands.

At operation 415, the processing device determines a count of zerosprogrammed in the LWP. Depending on the embodiment, the processingdevice can determine the count of zeros by reading data from the memorydevice or by reading threshold voltages of each cell in the LWP andcomparing the threshold voltages to a read level.

At operation 420, the processing device determines whether to perform adummy write operation on the LWP based on the count of zeros. Indetermining whether to perform the dummy write operation, the processingdevice compares the count of zeros programmed in the LWP to a thresholdconstraint. If the number of zeros satisfy the threshold constraint(e.g., if the number of zeros is greater than the threshold constraint),the processing device determines the LWP is sufficiently programmed andforgoes the dummy write operation (operation 430).

If the number of zeros does not satisfy the threshold constraint (e.g.,if the number of zeros is less than the threshold constraint), theprocessing device performs a dummy write operation on the LWP, atoperation 425. The dummy write operation includes writing dummy data tothe LWP.

As shown in FIG. 5 , the method 400 can, in some embodiments, includeoperations 505 and 510. As shown, operations 505 and 510 can beperformed as part of (e.g., sub-operations or a sub-routine) operation410, where the processing device determines a count of zeroes programmedin the LWP.

As noted above, the memory device can include multiple page types andeach page type has one or more associated default read levels. Atoperation 505, the processing device modifies a read level associatedwith the LWP. For example, the processing device can increasing a readlevel associated with the LWP relative to the default read level. Byincreasing the read level, the processing device increases the thresholdfor determining whether a memory cell threshold voltage represents azero. The processing device increases the read level to provideadditional margin to the system for detecting the number of programmedbits.

At operation 510, the processing device determines the number of zerosprogrammed in the LWP based on the modified read level. Morespecifically, the processing device determines a zero is programmed intoa particular cell based on a comparison of the threshold voltage of thecell to the modified read level. In particular, if threshold voltage ofthe cell is higher than the modified read level, the cell is recognizedas zero.

EXAMPLES

Example 1 is a memory sub-system comprising: a memory device comprisingat least one memory block comprising multiple pages; and a processingdevice, operatively coupled with the memory device, to performoperations comprising: detecting an asynchronous power loss event at thememory device; in response to detecting the asynchronous power lossevent, identifying a last written page from among the multiple pages;determining a count of zeroes programmed in the last written page; anddetermining whether to perform a dummy write operation at the lastwritten page based on the count of zeroes programmed in the last writtenpage.

Example 2 includes the memory sub-system of example 1, whereindetermining whether to perform the dummy write operation at the lastwritten page comprises comparing the count of zeroes programmed in thelast written page to a threshold constraint.

Example 3 includes the memory sub-system of any one of examples 1 and 2,wherein the operations comprise: performing a dummy write operation atthe last written page in response to determining the zeroes programmedin the last written page does not satisfy the threshold constraint, thedummy write operation comprising writing dummy data to the last writtenpage.

Example 4 includes the memory sub-system of any one of examples 1-3,wherein the operations comprise: foregoing the dummy write operation inresponse to determining the count of zeroes programmed in the lastwritten page satisfy the threshold constraint.

Example 5 includes the memory sub-system of any one of examples 1-4,wherein the determining of the count of zeroes programmed in the lastwritten page includes: comparing a threshold voltage of a cell in thelast written page to a read level associated with the last written pageto determine whether a zero is programmed in the cell.

Example 6 includes the memory sub-system of any one of examples 1-5,wherein the determining of the count of zeroes programmed in the lastwritten page includes: modifying a read level associated with the lastwritten page.

Example 7 includes the memory sub-system of any one of examples 1-6,wherein the determining of the count of zeroes programmed in the lastwritten page comprises: determining a zero is programmed in a cell ofthe last written page based on a comparison of a threshold voltage ofthe cell with the modified read level.

Example 8 includes the memory sub-system of any one of examples 1-7,wherein in the modifying of the read level associated with the lastwritten page includes decreasing the read level below a default readlevel.

Example 9 includes the memory sub-system of any one of examples 1-8,wherein the default read level associated with the last written page isbased on a page type of the last written page.

Example 10 is a method comprising: detecting an asynchronous power lossevent at a memory device comprising at least one memory block, the atleast one block comprising multiple pages; in response to detecting theasynchronous power loss event, identifying a last written page fromamong the multiple pages; determining a count of zeroes programmed inthe last written page; and determining whether to perform a dummy writeoperation at the last written page based on the count of zeroesprogrammed in the last written page

Example 11 includes the method of example 10, wherein determiningwhether to perform the dummy write operation at the last written pagecomprises comparing the count of zeroes programmed in the last writtenpage to a threshold constraint.

Example 12 includes the method of any one of examples 10-11, wherein theoperations comprise: performing a dummy write operation at the lastwritten page in response to determining the zeroes programmed in thelast written page does not satisfy the threshold constraint, the dummywrite operation comprising writing dummy data to the last written page.

Example 13 includes the method of any one of examples 10-12, wherein theoperations comprise: foregoing the dummy write operation in response todetermining the count of zeroes programmed in the last written pagesatisfy the threshold constraint.

Example 14 includes the method of any one of examples 10-13, wherein thedetermining of the count of zeroes programmed in the last written pageincludes: comparing a threshold voltage of a cell in the last writtenpage to a read level associated with the last written page to determinewhether a zero is programmed in the cell.

Example 15 includes the method of any one of examples 10-14, wherein thedetermining of the count of zeroes programmed in the last written pageincludes: modifying a read level associated with the last written page.

Example 16 includes the method of any one of examples 10-15, wherein thedetermining of the count of zeroes programmed in the last written pagecomprises: determining a zero is programmed in a cell of the lastwritten page based on a comparison of a threshold voltage of the cellwith the modified read level.

Example 17 includes the method of any one of examples 10-16, wherein inthe modifying of the read level associated with the last written pageincludes decreasing the read level below a default read level. whereinin the modifying of the read level associated with the last written pageincludes decreasing the read level below a default read level.

Example 18 is a computer-readable storage medium comprising instructionsthat, when executed by a processing device, configure the processingdevice to perform operations comprising: detecting an asynchronous powerloss event at a memory device comprising at least one memory block, theat least one block comprising multiple pages; in response to detectingthe asynchronous power loss event, identifying a last written page fromamong the multiple pages; determining a count of zeroes programmed inthe last written page; and comparing the count of zeroes programmed inthe last written page to a threshold constraint to determine whether toperform a dummy write operation at the last written page based on thecount of zeroes programmed in the last written page.

Example 19 includes the computer-readable storage medium of example 18,wherein the operations further comprise: performing a dummy writeoperation at the last written page in response to determining the zeroesprogrammed in the last written page does not satisfy the thresholdconstraint, the dummy write operation comprising writing dummy data tothe last written page.

Example 20 includes the computer-readable storage medium of any one ofexamples 18 and 19, wherein the operations further comprise: foregoingthe dummy write operation in response to determining the count of zeroesprogrammed in the last written page satisfy the threshold constraint.

FIG. 6 illustrates an example machine in the form of a computer system600 within which a set of instructions can be executed for causing themachine to perform any one or more of the methodologies discussedherein. FIG. 6 illustrates an example machine of a computer system 600within which a set of instructions, for causing the machine to performany one or more of the methodologies discussed herein, can be executed.In some embodiments, the computer system 600 can correspond to a hostsystem (e.g., the host system 120 of FIG. 1 ) that includes, is coupledto, or utilizes a memory sub-system (e.g., the memory sub-system 110 ofFIG. 1 ) or can be used to perform the operations of a controller (e.g.,to execute an operating system to perform operations corresponding tothe APL handling component 113 of FIG. 1 ). In alternative embodiments,the machine can be connected (e.g., networked) to other machines in alocal area network (LAN), an intranet, an extranet, and/or the Internet.The machine can operate in the capacity of a server or a client machinein client-server network environment, as a peer machine in apeer-to-peer (or distributed) network environment, or as a server or aclient machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box(STB), a Personal Digital Assistant (PDA), a cellular telephone, a webappliance, a server, a network router, a switch or bridge, or anymachine capable of executing a set of instructions (sequential orotherwise) that specify actions to be taken by that machine. Further,while a single machine is illustrated, the term “machine” shall also betaken to include any collection of machines that individually or jointlyexecute a set (or multiple sets) of instructions to perform any one ormore of the methodologies discussed herein.

The example computer system 600 includes a processing device 602, a mainmemory 604 (e.g., ROM, flash memory, DRAM such as SDRAM or RDRAM, etc.),a static memory 606 (e.g., flash memory, static random access memory(SRAM), etc.), and a data storage system 618, which communicate witheach other via a bus 630.

Processing device 602 represents one or more general-purpose processingdevices such as a microprocessor, a central processing unit, or thelike. More particularly, the processing device can be a complexinstruction set computing (CISC) microprocessor, reduced instruction setcomputing (RISC) microprocessor, very long instruction word (VLIW)microprocessor, or a processor implementing other instruction sets, orprocessors implementing a combination of instruction sets. Processingdevice 602 can also be one or more special-purpose processing devicessuch as an ASIC, a FPGA, a digital signal processor (DSP), networkprocessor, or the like. The processing device 602 is configured toexecute instructions 626 for performing the operations and stepsdiscussed herein. The computer system 600 can further include a networkinterface device 608 to communicate over a network 620.

The data storage system 618 can include a machine-readable storagemedium 624 (also known as a computer-readable medium) on which is storedone or more sets of instructions 626 or software embodying any one ormore of the methodologies or functions described herein. Theinstructions 626 can also reside, completely or at least partially,within the main memory 604 and/or within the processing device 602during execution thereof by the computer system 600, the main memory 604and the processing device 602 also constituting machine-readable storagemedia. The machine-readable storage medium 624, data storage system 618,and/or main memory 604 can correspond to the memory sub-system 110 ofFIG. 1 .

In one embodiment, the instructions 626 include instructions toimplement functionality corresponding to a data destruction component(e.g., the APL handling component 113 of FIG. 1 ). While themachine-readable storage medium 624 is shown in an example embodiment tobe a single medium, the term “machine-readable storage medium” should betaken to include a single medium or multiple media that store the one ormore sets of instructions. The term “machine-readable storage medium”shall also be taken to include any medium that is capable of storing orencoding a set of instructions for execution by the machine and thatcause the machine to perform any one or more of the methodologies of thepresent disclosure. The term “machine-readable storage medium” shallaccordingly be taken to include, but not be limited to, solid-statememories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presentedin terms of algorithms and symbolic representations of operations ondata bits within a computer memory. These algorithmic descriptions andrepresentations are the ways used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and generally,conceived to be a self-consistent sequence of operations leading to adesired result. The operations are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, combined, compared, and otherwise manipulated. It hasproven convenient at times, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. The presentdisclosure can refer to the action and processes of a computer system,or similar electronic computing device, that manipulates and transformsdata represented as physical (electronic) quantities within the computersystem's registers and memories into other data similarly represented asphysical quantities within the computer system memories or registers orother such information storage systems.

The present disclosure also relates to an apparatus for performing theoperations herein. This apparatus can be specially constructed for theintended purposes, or it can include a general-purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program can be stored in a computerreadable storage medium, such as, but not limited to, any type of diskincluding floppy disks, optical disks, CD-ROMs, and magnetic-opticaldisks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or anytype of media suitable for storing electronic instructions, each coupledto a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general-purposesystems can be used with programs in accordance with the teachingsherein, or it can prove convenient to construct a more specializedapparatus to perform the method. The structure for a variety of thesesystems will appear as set forth in the description below. In addition,the present disclosure is not described with reference to any particularprogramming language. It will be appreciated that a variety ofprogramming languages can be used to implement the teachings of thedisclosure as described herein.

The present disclosure can be provided as a computer program product, orsoftware, that can include a machine-readable medium having storedthereon instructions, which can be used to program a computer system (orother electronic devices) to perform a process according to the presentdisclosure. A machine-readable medium includes any mechanism for storinginformation in a form readable by a machine (e.g., a computer). In someembodiments, a machine-readable (e.g., computer-readable) mediumincludes a machine (e.g., a computer) readable storage medium such as aROM, RAM, magnetic disk storage media, optical storage media, flashmemory components, and so forth.

In the foregoing specification, embodiments of the disclosure have beendescribed with reference to specific example embodiments thereof. Itwill be evident that various modifications can be made thereto withoutdeparting from the broader scope of embodiments of the disclosure as setforth in the following claims. The specification and drawings are,accordingly, to be regarded in an illustrative sense rather than arestrictive sense.

What is claimed is:
 1. A system comprising: a memory device; and aprocessing device, operatively coupled with the memory device,configured to perform operations comprising: detecting an asynchronouspower loss event at the memory device; and in response to detecting theasynchronous power loss event, performing an asynchronous power lossrecovery process, the performing of the asynchronous power loss recoveryprocess comprising determining whether to write dummy data to a lastwritten page based on a number of zeroes programmed in the last writtenpage.
 2. The system of claim 1, wherein the performing asynchronouspower loss recovery process further comprises performing a dummy writeoperation at the last written page in response to determining the numberof zeroes programmed in the last written page does not satisfy athreshold constraint, the dummy write operation comprising writing thedummy data to the last written page.
 3. The system of claim 1, whereinthe performing asynchronous power loss recovery process furthercomprises foregoing a dummy write operation to write the dummy data tothe last written page in response to determining the number of zeroesprogrammed in the last written page satisfy a threshold constraint. 4.The system of claim 1, wherein the performing asynchronous power lossrecovery process further comprises determining the number of zeroesprogrammed in the last written page.
 5. The system of claim 4, whereinthe determining of the number of zeroes programmed in the last writtenpage includes: comparing a threshold voltage of a cell in the lastwritten page to a read level associated with the last written page todetermine whether a zero is programmed in the cell.
 6. The system ofclaim 4, wherein the determining of the number of zeroes programmed inthe last written page includes: modifying a read level associated withthe last written page.
 7. The system of claim 6, wherein the determiningof the number of zeroes programmed in the last written page comprises:determining a zero is programmed in a cell of the last written pagebased on a comparison of a threshold voltage of the cell with themodified read level.
 8. The system of claim 6, wherein in the modifyingof the read level associated with the last written page includesdecreasing the read level below a default read level.
 9. The system ofclaim 8, wherein the default read level associated with the last writtenpage is based on a page type of the last written page.
 10. A methodcomprising: detecting, by a processing device, an asynchronous powerloss event at a memory device; and in response to detecting theasynchronous power loss event, performing, by the processing device, anasynchronous power loss recovery process, the performing of theasynchronous power loss recovery process comprising determining whetherto write dummy data to a last written page based on a number of zeroesprogrammed in the last written page.
 11. The method of claim 10, whereinthe performing asynchronous power loss recovery process furthercomprises performing a dummy write operation at the last written page inresponse to determining the number of zeroes programmed in the lastwritten page does not satisfy a threshold constraint, the dummy writeoperation comprising writing the dummy data to the last written page.12. The method of claim 10, wherein the performing asynchronous powerloss recovery process further comprises foregoing a dummy writeoperation to write the dummy data to the last written page in responseto determining the number of zeroes programmed in the last written pagesatisfy a threshold constraint.
 13. The method of claim 10, wherein theperforming asynchronous power loss recovery process further comprisesdetermining the number of zeroes programmed in the last written page.14. The method of claim 13, wherein the determining of the number ofzeroes programmed in the last written page includes: comparing athreshold voltage of a cell in the last written page to a read levelassociated with the last written page to determine whether a zero isprogrammed in the cell.
 15. The method of claim 13, wherein thedetermining of the number of zeroes programmed in the last written pageincludes: modifying a read level associated with the last written page.16. The method of claim 15, wherein the determining of the number ofzeroes programmed in the last written page comprises: determining a zerois programmed in a cell of the last written page based on a comparisonof a threshold voltage of the cell with the modified read level.
 17. Themethod of claim 15, wherein in the modifying of the read levelassociated with the last written page includes decreasing the read levelbelow a default read level.
 18. The method of claim 17, wherein thedefault read level associated with the last written page is based on apage type of the last written page.
 19. A non-transitorycomputer-readable storage medium comprising instructions that, whenexecuted by a processing device, configure the processing device toperform operations comprising: detecting an asynchronous power lossevent at a memory device; and in response to detecting the asynchronouspower loss event, performing an asynchronous power loss recoveryprocess, the performing of the asynchronous power loss recovery processcomprising determining whether to write dummy data to a last writtenpage based on a number of zeroes programmed in the last written page.20. The non-transitory computer-readable storage medium of claim 19,wherein the performing asynchronous power loss recovery process furthercomprises: foregoing a dummy write operation to write the dummy data tothe last written page in response to determining the number of zeroesprogrammed in the last written page satisfy a threshold constraint.